Thread for random DIY-related questions

[FAP]

So you’re basically just putting a cap (or in this case looks like several) across +12v & common, like a DC filtering cap?
I’m confused what the switch is supposed to do; I can’t tell what J1 is supposed to be, either, let alone why there’d need to be a diode there.

[crochambeau]

So you’re basically just putting a cap (or in this case looks like several) across +12v & common, like a DC filtering cap?
I’m confused what the switch is supposed to do; I can’t tell what J1 is supposed to be, either, let alone why there’d need to be a diode there.

That's a power switch. I did not draw something up to answer your question, I simply grabbed a screen shot of an existing schematic in which I use the tactic I recommend. It happens to have more features than discussed in this topic because that's the way it's built.

J1 is the connector for DC input. The diode is there to prevent damage if someone plugs in a power supply of improper polarity. Test points are there so I can easily scope the rails in case something is sideways.

So yeah, the important bits are: main DC inlet has a capacitor, and each of the stages you want to prevent crosstalk have some buffering aspect like a resistor, followed by another capacitor.

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Example: the circuit hanging off leg #1 is pulling on the power supply the hardest. In order for those ripples to reach the weaker circuit on branch 2, it must overspill the capacitor (in this case C3) which is "walled in" by the resistor R4, overtop capacitor C1, which is both supplied by the main DC supply AND "walled in" by R5 and overtop capacitor C4 before reaching circuit 2. This is a low tech method that will only really work in circuits that do not draw lots of power. It IS possible to drive a 555 hard enough that this low tech method may not be that effective. If you're heating up ICs, you'd probably want to use actual voltage regulators to keep the stages from controlling each other (though I would argue that if you're heating up ICs doing OSC duty, a redesign may be in order).

Anyway, here's a rough idea of how I employ this in my design. The different colors are the different branches.

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This concept may work to address your issue. It may not. I may be throwing red herrings at you based on shit I've run into that does not apply.

[FAP]

Well herring or not, I always learn something new from one of your walkthroughs, so thanks for that! I’ll have to try it later.
If you’re curious, this came about from me trying to breadboard multiple LFOs, quick & dirty, for use to modulate another project. Eventually I ought to make a big box of these things but I don’t want to commit to the “whole package” just yet.

[crochambeau]

Honestly, if this is breadboard behavior it might just be bad grounding or some flying wire crosstalk. If you've got a neat, relatively short wire layout and it's still misbehaving (or if you're wanting to lay out a PCB) building this stuff into it may be helpful, but I never trust breadboard to represent reality hahaha.

My pleasure, I'm happy if my rambling improves anything anywhere. Onward and upward!

[FAP]

So good news bad news: I’ll start with the former.
Adding the buffering components to each ”stage” (more like “copy” but semantics be damned) did yield a significant improvement in crosstalk mitigation. As an aside, I had unknowingly applied a similar principle when I built the cacodemon last year, so in retrospect it makes sense.

That said, crosstalk wasn’t entirely eliminated and I imagine the problem only gets more pronounced with each additional stage added. I used 100ohms for the resistors and 10uf for the caps: would increasing or decreasing the farads result in better results?

If nothing else, I’ve gained a newfound skepticism of breadboards. It wasn’t too long ago I paid like 100 fucking dollars for one of these things hoping it’d be a step up from the boards I’d salvaged from college: turns out there’s a few spots that are bent out of shape on it, too. Quite frustrating.

Do you think this same crosstalk/coupling phenomenon would occur with op-amp based designs,!or is this something peculiar to timers like the 555?

[crochambeau]

Crosstalk is a feature of long, parallel runs. Could be the structure of the breadboard, could be long wires, could be poor grounding. Could be something else we're overlooking entirely.

Upping the capacitor value is worth experimenting with. You can also measure voltage across the resistor, that will give you an idea of how much sizing you can do there as well.

o-scopes are wonderful tools for sniffing around issues like this, as once you can see the ripple, or spike that is causing triggering elsewhere, snubbing it becomes a matter of trying different things and watching the scope.

Proximity of storage cap to the 555 timer may also make a difference, keep those lines short.

crosstalk and instability can plague opamps as well, the more gain you run the touchier things can be.

[Indeterminacy]

Honestly, if this is breadboard behavior it might just be bad grounding or some flying wire crosstalk. If you've got a neat, relatively short wire layout and it's still misbehaving (or if you're wanting to lay out a PCB) building this stuff into it may be helpful, but I never trust breadboard to represent reality hahaha.

My pleasure, I'm happy if my rambling improves anything anywhere. Onward and upward!

Curtis points out what was drilled into my head over and over when I worked
in Big Tech in the mid-90s. ( Token rings were fun btw and why did mainframes
use 400hz power? Made a lot for sense for mobile radar. )

[FAP]

I'm back again, with a few questions:

1. I'm designing something where I want to be able to toggle between buffered bypass & true bypass. I haven't breadboarded this yet, but I'd like some feedback on my schematic (see above). The idea is to use an op-amp (e.g. TL071) to act as the active buffer; the input signal is fed through the op-amp at all times, but a toggle switch determines whether it's the output signal from the op-amp that goes through to the next stage, or if it gets shunted to gnd and instead it's the original input signal that goes through. Does this look okay i.e. will this work?

2. I included both an input and output buffer (basically the same circuit for both): do I need both an input and output buffer or is one sufficient?

3. Part of the reason why there's two buffers here (see previous question) is because my earlier designs used the inverting input of the op-amp instead of the non-inverting input. The idea was that, if I had to use the inverting input for whatever reason, I'd need a second buffer to correct the phase (negative plus negative equals positive). In theory, this would also have the benefit of being able to flip the phase by simply turning one of the buffers off (negative plus positive equals negative). Is this correct?

4. I want to eliminate waveform offset as much as possible. From what I understand, this necessitates some kind of bipolar power setup e.g. ±9v instead of just 9vDC. Is this correct, and if so, would something like this work:

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5. If there's a better option than the discrete rail splitter circuit (see previous question), please post it!

Much thanks.

[crochambeau]

I'm back again, with a few questions:



1. I'm designing something where I want to be able to toggle between buffered bypass & true bypass.

There is no bypass of any sort depicted in this image, am I supposed to assume that bypass is a function within the DUT? If so, you're only adding a buffer into the signal path, which could be done as a bog standard bypassed stage in conjunction with a straight wire bypass.

I don't like to run the output of any active into a dead short. I know the TL07n protect against dead shorts, but I feel like designing IN a dead short condition as a standard mode is very messy practice, and I therefore discourage it. I don't have first hand measurements to back this up, but I'd expect the power draw to go up in dead short conditions.

The converse is that once you add resistance in line, you're entering signal loss territory and recovery gain becomes a consideration IF the resistor is in the signal path. You could circumvent this by placing resistance in line with "ground" on your scheme.

There's no need to cascade buffers if all you're after is a unity gain bypass.

I'm not sure what your intent is behind this approach. Bench fixture for observing circuit behavior in different signal state conditions?

With respect to single rail versus bipolar power, the interior of an opamp ignores the conditions and only "knows" what power range is available across the Vcc & Vee pins, and how the incoming signal relates within the headroom thus defined.

I have a suspicion that most all issues one has with a single rail design is due to:
1) imperfect common voltage characteristics predistorting the signal.
2) relatively low headroom offered by the (typically) nine volt headroom
3) reliance of DC blocking capacitors on both input and output of circuit in order to maintain compatibility with the outside world.

4. I want to eliminate waveform offset as much as possible. From what I understand, this necessitates some kind of bipolar power setup e.g. ±9v instead of just 9vDC. Is this correct, and if so, would something like this work:

If this is being fed from a battery, the battery is essentially floating, and the virtual ground could be tied to actual ground. If it's fed from a power supply, actual ground is tied to one of those rails and the virtual ground is a DC potential somewhere between the extremes of the power supply. That would require DC blocking capacitors.

I've been using a 34063 based SMPS stage to produce a -9 volt rail in my self contained bipolar builds. It is not the simplest path, and it's not without issues (when multiple instances are present). So I'm not going to recommend it as a silver bullet, BUT - if you have bipolar power, you can DC couple your signal path and just ground reference it with minimal concern of DC bias or waveform degradation.